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1 ds05-10195-2e fujitsu semiconductor data sheet memory cmos 2 m 8 bits hyper page mode dynamic ram mb81v17805a-60/60l/-70/70l cmos 2,097,152 8 bits hyper page mode dynamic ram n description the fujitsu mb81v17805a is a fully decoded cmos dynamic ram (dram) that contains 16,777,216 memory cells accessible in 8-bit increments. the mb81v17805a features a ?yper page mode of operation whereby high-speed random access of up to 1024 8-bits of data within the same row can be selected. the mb81v17805a dram is ideally suited for mainframe, buffers, hand-held computers video imaging equipment, and other memory applications where very low power dissipation and high bandwidth are basic requirements of the design. since the standby current of the mb81v17805a is very small, the device can be used as a non-volatile memory in equipment that uses batteries for primary and/or auxiliary power. the mb81v17805a is fabricated using silicon gate cmos and fujitsus advanced four-layer polysilicon and two- layer aluminum process. this process, coupled with advanced stacked capacitor memory cells, reduces the possibility of soft errors and extends the time interval between memory refreshes. clock timing requirements for the mb81v17805a are not critical and all inputs are lvttl compatible. n product line & features parameter mb81v17805a -60 -60l -70 -70l ras access time 60 ns max. 70 ns max. random cycle time 104 ns min. 124 ns min. address access time 30 ns max. 35 ns max. c as access time 15 ns max. 17 ns max. hyper page mode cycle time 25 ns min. 30 ns min. low power dissipation operating current 432 mw max. 396 mw max. standby current lvttl level 3.6 mw max. 3.6 mw max. 3.6 mw max. 3.6 mw max. cmos level 1.8 mw max. 0.54 mw max. 1.8 mw max. 0.54 mw max. this device contains circuitry to protect the inputs against damage due to high static voltages or electric ?lds. however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. 2,097,152words 8 bits organization silicon gate, cmos, advanced capacitor cell all input and output are lvttl compatible 2,048 refresh cycles every 32.8 ms self refresh function standard and low power versions early write or oe controlled write capability ras -only, cas -before-ras , or hidden refresh hyper page mode, read-modify-write capability on chip substrate bias generator for high performance
2 mb81v17805a-60/-60l/-70/-70l n absolute maximum ratings (see warning) warning: permanent device damage may occur if the above absolute maximum ratings are exceeded. func- tional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. n package parameter symbol value unit voltage at any pin relative to v ss v in , v out ?.5 to +4.6 v voltage of v cc supply relative to v ss v cc ?.5 to +4.6 v power dissipation p d 1.0 w short circuit output current i out ?0 to +50 ma operating temperature t ope 0 to +70 c storage temperature t stg ?5 to +125 c (lcc-28p-m07) package and ordering information 28-pin plastic (400mil) soj, order as mb81v17805a- pj 28-pin plastic (400mil) tsop-ii with normal bend leads, order as mb81v17805a- pftn and mb81v17805a- lpftn (low power) (fpt-28p-m14) (normal bend) plastic soj package plastic tsop package
3 mb81v17805a-60/-60l/-70/-70l n capacitance (t a = 25 c, f = 1 mhz) parameter symbol max. unit input capacitance, a 0 to a 11 c in1 5pf input capacitance, ras , cas , we , oe c in2 5pf input/output capacitance, dq 1 to dq 8 c dq 7pf fig. 1 ? mb81v17805a dynamic ram - block diagram cas ras we oe v cc v ss a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 9 a 10 mode control write clock gen clock gen #2 column decoder clock gen #1 sense ampl & i/o gate 16,777,216 bit storage cell address buffer & pre- decoder refresh address counter row decoder substrate bias gen dq 1 to dq 8 data out buffer data in buffer
4 mb81v17805a-60/-60l/-70/-70l n pin assignments and descriptions designator 28-pin soj (top view) 28-pin tsop (top view) we oe function a 0 to a 10 address inputs row : a 0 to a 10 column : a 0 to a 9 refresh : a 0 to a 10 ras row address strobe cas column address strobe write enable output enable dq 1 to dq 8 data input/output v cc +3.3 volt power supply v ss circuit ground n.c. no connection 1 pin index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 pin index v cc dq 1 dq 2 dq 3 dq 4 v ss v ss dq 8 dq 7 dq 6 dq 5 we ras a10 a 0 a 1 a 2 a 3 v cc cas oe a 9 a 8 a 7 a 6 a 5 a 4 v cc dq 1 dq 2 dq 3 dq 4 v ss v ss dq 8 dq 7 dq 6 dq 5 we ras a 10 a 0 a 1 a 2 a 3 v cc cas oe a 9 a 8 a 7 a 6 a 5 a 4 n.c. n.c.
5 mb81v17805a-60/-60l/-70/-70l n recommended operating conditions * : undershoots of up to ?.0 volts with a pulse width not exceeding 20 ns are acceptable. n functional operation address inputs twenty-one input bits are required to decode any sixteen of 16,777,216 cell addresses in the memory matrix. since only eleven address bits (a 0 to a 10 ) are available, the column and row inputs are separately strobed by cas and ras as shown in figure 1. first, eleven row address bits are input on pins a 0 -through-a 10 and latched with the row address strobe (ras ) then, ten column address bits are input and latched with the column address strobe (cas ). both row and column addresses must be stable on or before the falling edges of ras and cas , respectively. the address latches are of the flow-through type; thus, address information appearing after t rah (min) + t t is automatically treated as the column address. write enable the read or write mode is determined by the logic state of we . when we is active low, a write cycle is initiated; when we is high, a read cycle is selected. during the read mode, input data is ignored. data input input data is written into memory in either of three basic ways : an early write cycle, an oe (delayed) write cycle, and a read-modify-write cycle. the falling edge of we or cas , whichever is later, serves as the input data-latch strobe. in an early write cycle, the input data is strobed by cas and the setup/hold times are referenced to cas because we goes low before cas . in a delayed write or a read-modify-write cycle, we goes low after cas ; thus, input data is strobed by we and all setup/hold times are referenced to the write-enable signal. data output the three-state buffers are lvttl compatible with a fanout of one ttl load. polarity of the output data is identical to that of the input; the output buffers remain in the high-impedance state until the column address strobe goes low. when a read or read-modify-write cycle is executed, valid outputs and high-z state are obtained under the following conditions: t rac : from the falling edge of ras when t rcd (max) is satisfied. t cac : from the falling edge of cas when t rcd is greater than t rcd (max). t aa : from column address input when t rad is greater than t rad (max), and t rcd (max) is satisfied. t oea : from the falling edge of oe when oe is brought low after t rac , t cac , or t aa . t oez : from oe inactive. t off : from cas inactive while ras inactive. t ofr : from ras inactive while cas inactive. t wez : from we active while cas inactive. the data remains valid after either oe is inactive, or both ras and cas are inactive, or cas is reactived. when an early write is executed, the output buffers remain in a high-impedance state during the entire cycle. parameter notes symbol min. typ. max. unit ambient operating temp. supply voltage *1 v cc 3.0 3.3 3.6 v 0 c to +70 c v ss 000 input high voltage, all inputs *1 v ih 2.0 v cc +0.3 v input low voltage, all inputs* *1 v il ?.3 0.8 v
6 mb81v17805a-60/-60l/-70/-70l hyper page mode of operation the hyper page mode operation provides faster memory access and lower power dissipation. the hyper page mode is implemented by keeping the same row address and strobing in successive column addresses. to satisfy these conditions, ras is held low for all contiguous memory cycles in which row addresses are common. for each page of memory (within column address locations), any of 1,024 8-bits can be accessed and, when multiple mb81v17805as are used, cas is decoded to select the desired memory page. hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted. hyper page mode features that output remains valid when cas is inactive until cas is reactivated.
7 mb81v17805a-60/-60l/-70/-70l n dc characteristics (at recommended operating conditions unless otherwise noted.) note 3 parameter notes symbol conditions value unit min. typ. max. std power low power output high voltage *1 v oh i oh = ?.0 ma 2.4 v output low voltage *1 v ol i ol = +2.0 ma 0.4 0.4 input leakage current (any input) i i(l) 0 v v in v cc ; 3.0 v v cc 3.6 v; v ss = 0 v; all other pins not under test = 0 v ?0 10 10 m a output leakage current i dq(l) 0 v v out v cc ; data out disabled ?0 10 10 operating current (average power supply current) *2 mb81v17805a -60/60l i cc1 ras & cas cycling; t rc = min. 120 120 ma mb81v17805a -70/70l 110 110 standby current (power supply current) *2 lvttl level i cc2 ras = cas = v ih 1.0 1.0 ma cmos level ras = cas 3 v cc ?.2 v 500 150 m a refresh current#1 (average power supply current) *2 mb81v17805a -60/60l i cc3 cas = v ih , ras cycling; t rc = min. 120 120 ma mb81v17805a -70/70l 110 110 hyper page mode curren *2 mb81v17805a -60/60l i cc4 ras = v il , cas cycling; t hpc = min. 120 120 ma mb81v17805a -70/70l 110 110 refresh current#2 (average power supply current) *2 mb81v17805a -60/60l i cc5 ras cycling; cas -before-ras ; t rc = min. 120 120 ma mb81v17805a -70/70l 110 110 battery back up current (average power supply current) *2 mb81v17805a -60/70 i cc6 ras cycling; cas -before-ras ; t rc = 16 m s t ras = min. to 300 ns v ih 3 v cc ?.2 v, v il 0.2 v 1000 m a mb81v17805a -60l/70l ras cycling; cas -before-ras ; t rc = 62.5 m s t ras = min. to 300 ns v ih 3 v cc ?.2 v, v il 0.2 v 300 refresh current#3 (average power supply current) mb81v17805a -60/60l i cc9 ras = v il , cas = v il self refresh; 1000 250 m a mb81v17805a -70/70l
8 mb81v17805a-60/-60l/-70/-70l n ac characteristics (at recommended operating conditions unless otherwise noted.) notes 3, 4, 5 (continued) no. parameter notes symbol mb81v17805a-60/ 60l mb81v17805a-70/ 70l unit min. max. min. max. 1 time between refresh standard t ref 32.8 32.8 ms low power 128 128 2 random read/write cycle time t rc 104 124 ns 3 read-modify-write cycle time t rwc 138 162 ns 4 access time from ras *6,9 t rac ?0?0ns 5 access time from cas *7,9 t cac ?5?7ns 6 column address access time *8,9 t aa ?0?5ns 7 output hold time t oh 3?ns 8 output hold time from cas t ohc 5?ns 9 output buffer turn on delay time t on 0?ns 10 output buffer turn off delay time *10 t off ?5?7ns 11 output buffer turn off delay time from ras *10 t ofr ?5?7ns 12 output buffer turn off delay time from we *10 t wez ?5?7ns 13 transition time t t 150150ns 14 ras precharge time t rp 40?0ns 15 ras pulse width t ras 60 100000 70 100000 ns 16 ras hold time t rsh 15?7ns 17 cas to ras precharge time *21 t crp 5?ns 18 ras to cas delay time *11,12,22 t rcd 14 45 14 53 ns 19 cas pulse width t cas 10?3ns 20 cas hold time t csh 40?0ns 21 cas precharge time (normal) *19 t cpn 10?0ns 22 row address set up time t asr 0?ns 23 row address hold time t rah 10?0ns 24 column address set up time t asc 0?ns 25 column address hold time t cah 10?0ns 26 column address hold time from ras t ar 24?4ns 27 ras to column address delay time *13 t rad 12 30 12 35 ns 28 column address to ras lead time t ral 30?5ns 29 column address to cas lead time t cal 23?8ns 30 read command set up time t rcs 5?ns
9 mb81v17805a-60/-60l/-70/-70l (continued) no. parameter notes symbol mb81v17805a-60/ 60l mb81v17805a-70/ 70l unit min. max. min. max. 31 read command hold time referenced to ras *14 t rrh 0?ns 32 read command hold time referenced to cas *14 t rch 0?ns 33 write command set up time *15,20 t wcs 0?ns 34 write command hold time t wch 10?0ns 35 write hold time from ras t wcr 24?4ns 36 we pulse width t wp 10?0ns 37 write command to ras lead time t rwl 15?7ns 38 write command to cas lead time t cwl 10?3ns 39 din set up time t ds 0?ns 40 din hold time t dh 10?0ns 41 data hold time from ras t dhr 24?4ns 42 ras to we delay time *20 t rwd 77?9ns 43 cas to we delay time *20 t cwd 32?6ns 44 column address to we delay time *20 t awd 47?4ns 45 ras precharge time to cas active time (refresh cycles) t rpc 5?ns 46 cas set up time for cas -before- ras refresh t csr 0?ns 47 cas hold time for cas -before- ras refresh t chr 10?2ns 48 access time from oe *9 t oea ?5?7ns 49 output buffer turn off delay from oe *10 t oez ?5?7ns 50 oe to ras lead time for valid data t oel 10?0ns 51 oe to cas lead time t col 5?ns 52 oe hold time referenced to we *16 t oeh 5?ns 53 oe to data in delay time t oed 15?7ns 54 ras to data in delay time t rdd 15?7ns 55 cas to data in delay time t cdd 15?7ns 56 din to cas delay time *17 t dzc 0?ns 57 din to oe delay time *17 t dzo 0?ns 58 oe precharge time t oep 8?ns
10 mb81v17805a-60/-60l/-70/-70l (continued) no. parameter notes symbol mb81v17805a-60/ 60l mb81v17805a-70/ 70l unit min. max. min. max. 59 oe hold time referenced to cas t oech 10?0ns 60 we precharge time t wpz 8?ns 61 we to data in delay time t wed 15?7ns 62 hyper page mode ras pulse width t rasp 100000 100000 ns 63 hyper page mode read/write cycle time t hpc 25?0ns 64 hyper page mode read-modify-write cycle time t hprwc 69?9ns 65 access time from cas precharge *9,18 t cpa ?5?0ns 66 hyper page mode cas precharge time t cp 10?0ns 67 hyper page mode ras hold time from cas precharge t rhcp 35?0ns 68 hyper page mode cas precharge to we delay time t cpwd 52?9ns
11 mb81v17805a-60/-60l/-70/-70l notes: *1. referenced to v ss . *2. i cc depends on the output load conditions and cycle rates; the specified values are obtained with the output open. i cc depends on the number of address change as ras = v il cas = v ih and v il > ?.3 v. i cc1 , i cc3 i cc4 and i cc5 are specified at one time of address change during ras = v il and cas = v ih i cc2 is specified during ras = v ih and v il > ?.3 v. i cc6 is measured on condition that all address signals are fixed steady state. *3. an initial pause (ras = cas = v ih ) of 200 m s is required after power-up followed by any eight ras - only cycles before proper device operation is achieved. in case of using internal refresh counter, a minimum of eight cas -before-ras initialization cycles instead of 8 ras cycles are required. *4. ac characteristics assume t t = 2 ns. *5. input voltage levels are 0 v and 3 v, and input reference levels are v ih (min) and v il (max) for measuring timing of input signals. also, the transition time(t t ) is measured between v ih (min)and v il (max). the output reference levels are v oh = 2.0 v and v ol = 0.8 v. *6. assumes that t rcd t rcd (max), t rad t rad (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will be increased by the amount that t rcd exceeds the value shown. refer to fig.2 and 3. *7. if t rcd 3 t rcd (max), t rad 3 t rad (max), and t asc 3 t aa - t cac - t t , access time is t cac . *8. if t rad 3 t rad (max) and t asc t aa - t cac - t t , access time is t aa . *9. measured with a load equivalent to one ttl load and 100 pf. *10. t ofr, t wez, t off and t oez are specified that output buffer change to high impedance state. *11. operation within the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, access time is controlled exclusively by t cac or t aa . *12. t rcd (min) = t rah (min) + 2t t + t asc (min). *13. operation within the t rad (max) limit ensures that t rac (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, access time is controlled exclusively by t cac or t aa . *14. either t rrh or t rch must be satisfied for a read cycle. *15. t wcs is specified as a reference point only. if t wcs 3 t wcs (min) the data output pin will remain high-z state through entire cycle. *16. assumes that t wcs < t wcs (min). *17. either t dzc or t dzo must be satisfied. *18. t cpa is access time from the selection of a new column address (that is caused by changing both cas from ??to ??. therefore, if t cp is long, t cpa is longer than t cpa (max). *19. assumes that cas -before-ras refresh. *20. t wcs , t cwd , t rwd and t awd are not restrictive operating parameters. they are included in the data sheet as an electrical characteristic only. if t wcs > t wcs (min), the cycle is an early write cycle and d out pin will maintain high-impedance state through out the entire cycle. if t cwd > t cwd (min), t rwd > t rwd (min), and t awd > t awd (min), the cycle is a read-modify-write cycle and data from the selected cell will appear at the d out pin. if neither of the above conditions is satisfied, the cycle is a delayed write cycle and invalid data will appear the d out pin, and write operation can be executed by satisfying t rwl , t cwl , and t ral specifications. *21. the last cas rising edge. *22. the ?st cas falling edge.
12 mb81v17805a-60/-60l/-70/-70l n functional truth table x : ? or ? * : it is impossible in hyper page mode. operation mode clock input address input data i/o refresh note ras cas we oe row column input output standby h h x x high-z read cycle l l h l valid valid valid yes* t rcs 3 t rcs (min) write cycle (early write) l l l x valid valid valid high-z yes* t wcs 3 t wcs (min) read-modify- write cycle llh ? ll ? h valid valid valid valid yes* ras -only refresh cycle l h x x valid high-z yes cas -before-ras refresh cycle l l x x high-z yes t csr 3 t csr (min) hidden refresh cycle h ? l lh ? x l valid yes previous data is kept fig. 4 ? t cpa vs. t cp t rac (ns) t rcd (ns) t rad (ns) t cp (ns) fig. 2 ? t rac vs. t rcd fig. 3 ? t rac vs. t rad t rac (ns) t cpa (ns) 60 40 100 80 120 20 060 40 100 80 70ns version 60ns version 60 50 80 70 90 20 040 30 60 50 70ns version 40 30 60 50 70 10 030 20 50 40 60ns version 60ns version 70ns version 10
13 mb81v17805a-60/-60l/-70/-70l t rc t ras t ar t rp t cdd t rcd t crp t asr t rah t asc t cah t oel t rch t rrh t rcs t dzc t oea t dzo t on t oed t oh t off t rad t ral t cal t aa t cac t rac t oh t csh t rsh t cas t on t rdd t wpz t wed t wez valid data t oez t col description to implement a read operation, a valid address is latched by the ras and cas address strobes and with we set to a high level and oe set to a low level, the output is valid once the memory access time has elapsed. dq 1 to dq 8 pins are valid when ras and cas are high or until oe goes high. the access time is determined by ras (t rac ), cas (t cac ), oe (t oea ) or column addresses (t aa ) under the following conditions: if t rcd > t rcd (max), access time = t cac . if t rad > t rad (max), access time = t aa. if oe is brought low after t rac , t cac , or t aa (whichever occurs later), access time = t oea . however, if either cas or oe goes high, the output returns to a high-impedance state after t oh is satis?d. fig. 5 ? read cycle ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe column add row add high-z high-z ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
14 mb81v17805a-60/-60l/-70/-70l t rc t ras t rp t csh t rcd t crp t cas t asr t rah t asc t cah t wcr t wcs t wch t dh t ds t rsh t ar t dhr description a write cycle is similar to a read cycle except we is set to a low state and oe is an ? or ? signal. a write cycle can be implemented in either of three ways ?early write, delayed write, or read-modify-write. during all write cycles, timing parameters t rwl , t cwl , t ral and t cal must be satis?d. in the early write cycle shown above t wcs satis?d, data on the dq pins are latched with the falling edge of cas and written into memory. fig. 6 ? early write cycle column add row add high-z valid data in ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
15 mb81v17805a-60/-60l/-70/-70l t rc t ras t rcd t asr t cah t rcs t dzc invalid data t rp t asc t rah t cwl t wp t ds t dh t oed t dzo t oeh t wch t rwl t on t on t csh t cas t rsh t ar t crp t oez description in the delayed write cycle, t wcs is not satis?d; thus, the data on the dq pins are latched with the falling edge of we and written into memory. the output enable (oe ) signal must be changed from low to high before we goes low (t oed + t t + t ds ). fig. 7 ? delayed write cycle (oe controlled) row add col add high-z high-z valid data i n ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe high-z ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
16 mb81v17805a-60/-60l/-70/-70l t rwc t ras t rcd t asr t cah t rwl t rcs t rp t asc t rah t cwl t ds t dh t oed t dzo t oeh t rad t cwd t oez t oh t rwd t awd t dzc t cac t rac t aa t ar t crp t wp t on t oea t on fig. 8 ? read-modify-write-cycle description the read-modify-write cycle is executed by changing we from high to low after the data appears on the dq pins. in the read- modify-write cycle, oe must be changed from low to high after the memory access time. ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe valid row high-z high-z high-z add col add valid data i n ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) data
17 mb81v17805a-60/-60l/-70/-70l during one cycle is achieved, the input/output timing apply the same manner as the former cycle. t rasp t asc t rhcp t rp t rcd t cas t rsh t hpc t cas t cas t cp t rch t rcs t rch t rcs t dzc t cpa t cah t ar t cah t rah t asc t rrh t cah t asc t rch valid data t on t cac t on t aa t rad t csh t ral t dzo t aa t rac t rdd t ofr t off t oh t cpa t oh t on t ohc t cac t ohc t cdd t oed t oez t asr t crp t oh description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. fig. 9 ? hyper page mode read cycle ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe add row add col add col add high-z high-z t rcs col ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
18 mb81v17805a-60/-60l/-70/-70l t rasp t asr t asc t rcs t rhcp t rp t rcd t cas t rsh t hpc t cas t cas t cp t dzc t cah t cah t rah t rrh t cah t asc t rch valid data t cac t aa t rad t csh t ral high-z t ofr t off t oh t oez t oed t oh t oh t aa t cpa t cac t aa t on t oea t oep t oech t oez t oh t oez t oea t dzo t on t rac t cp t cal t cdd t col t oea t cac t cpa t ohc t crp t rdd t oh fig. 10 ? hyper page mode read cycle (oe = ? or ?? description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. high-z col high-z add row add col add col add ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe during one cycle is achieved, the input/output timing apply the same manner as the former cycle. high-z t asc ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
19 mb81v17805a-60/-60l/-70/-70l description the hyper page mode of operation permits faster successive memory operations at multiple column locations of the same row address. this operation is performed by strobing in the row address and maintaining ras at a low level and we at a high level during all successive memory cycles in which the row address is latched. the address time is determined by t cac , t aa , t cpa , or t oea , whichever one is the latest in occurring. t rasp t asc t rcs t rhcp t rp t cas t rsh t hpc t cas t cas t dzc t cah t cah t rah t asc t cah t asc t rch valid data t cac t aa t csh t ral t off t oh t oez t oed t oh t oh t aa t cac t aa t oea t dzo t on t rac t rcd t ofr t rcs t rch t wpz t rcs t rch t cal t wez t cac t on t on t wez t wpz t cdd t wed t wez t on t rad t crp t asr t rdd t wpz fig. 11 ? hyper page mode read cycle (we = ? or ?? high-z col high-z high-z add col add col add row add ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe during one cycle is achieved, the input/output timing apply the same manner as the former cycle. ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
20 mb81v17805a-60/-60l/-70/-70l t rasp t rp t rsh t hpc t rcd t csh t cas t asc t cah t cas t cp t cah t asc t cah t wcs t wch t wcs t wch t wcs t wch t ds t dh t asc t ds t dh t ds t dh t ar t wcr t dhr t rhcp t ral t cwl t cwl t rwl t asr t rah t crp t cwl t cas fig. 12 ? hyper page mode early write cycle row add high-z description the hyper page mode early write cycle is executed in the same manner as the hyper page mode read cycle except the states of we and oe are reversed. data appearing on the dq pins are latched on the falling edge of cas and the data is written into the memory. during the hyper page mode early write cycle, including the delayed (oe ) write and read-modify-write cycles, t cwl must be satis?d. col add col add col add valid data valid data valid data ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) during one cycle is achieved, the input/output timing apply the same manner as the former cycle. ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
21 mb81v17805a-60/-60l/-70/-70l description the hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of we and oe . input data on the dq pins are latched on the falling edge of we and written into memory. in the hyper page mode delayed write cycle, oe must be changed from low to high before we goes low (t oed + t t + t ds ). valid valid col add col add row add data i n data i n fig. 13 ? hyper page mode delayed write cycle t rasp t rp t hpc t rsh t cas t cas t cp t csh t rcd t crp t asr t rah t ar t asc t cah t asc t cah t cwl t rwl t wch t wp t cwl t wch t rcs t wp t dzc t ds t dh t dh t ds t oed t on t on t oed t oeh t on t dzo t oez t on t oez t oeh high-z ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) valid data
22 mb81v17805a-60/-60l/-70/-70l valid col add col add row add col add data i n fig. 14 ? hyper page mode read/write mixed cycle description the hyper page mode performs read/write operations repetitively during one ras cycle. at this time, t hpc (min) is invalid. high-z high-z high-z t rasp t rhcp t rp t rsh t cas t cas t hpc t cas t rcd t csh t crp t cp t rad t asr t asc t rah t cal t cah t asc t cah t asc t ral t cah t rcs t rch t wcs t wch t dh t ds t wed t dzc t rac t aa t cac t ohc t cac t wez t aa t cpa t on t dzo t on t oea t oed t oez ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe t cal ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) valid data
23 mb81v17805a-60/-60l/-70/-70l t cwl valid valid col add row add col add fig. 15 ? hyper page mode read-modify-write cycle high-z description during the hyper page mode of operation, the read-modify-write cycle can be executed by switching we from high to low after input data appears at the dq pins during a normal cycle. t rasp t rp t crp t rcd t cwd t rwl t hprwc t cwd t cp t asc t cah t asc t cah t rad t rah t asr t rcs t awd t cwl t rcs t wp t wp t ds t dh t dh t ds t rwd t dzc t oed t cac t aa t on t on t aa t cac t oed t on t on t rac t dzo t oea t cpa t oeh t oez t oea t oeh t oez ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) valid data data data t cpwd
24 mb81v17805a-60/-60l/-70/-70l t rc t rp t asr t rpc t rah t crp t ras t off t crp t oh fig. 16 ? ras -only refresh (we = oe = ? or ?? fig. 17 ? cas -before-ras refresh (addresses = we = oe = ? or ?? row address description refresh of ram memory cells is accomplished by performing a read, a write, or a read-modify-write cycle at each of 2048 row addresses every 32.8-milliseconds. three refresh modes are available: ras -only refresh, cas -before-ras refresh, and hidden refresh. ras -only refresh is performed by keeping ras low and cas high throughout the cycle; the row address to be refreshed is latched on the falling edge of ras . during ras -only refresh, dq pins are kept in a high-impedance state. description cas -before-ras refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. if cas is held low for the speci?d setup time (t csr ) before ras goes low, the on-chip refresh control clock generators and refresh address counter are enabled. an internal refresh operation automatically occurs and the refresh address counter is internally incremented in prep- aration for the next cas -before-ras refresh operation. high-z ras v ih v il v ih v il v ih v il v oh v ol cas dq (output) a 0 to a 10 t rc t ras t rpc t cpn t csr t chr t rp t off t oh t csr t cpn ras v ih v il v ih v il v oh v ol cas dq (output) high-z ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
25 mb81v17805a-60/-60l/-70/-70l t rc t rp t chr t rc t ras t ras t rp t oel t rsh t rah t asc t cah t rcs t rrh t cac t dzc t cdd t dzo t oea t oed t oez t crp t asr t oh t off t on t rcd t ral t ar t aa t rac t ofr t oh t rad fig. 18 ? hidden refresh cycle row address description a hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of cas and cycling ras . the refresh row address is provided by the on-chip refresh address counter. this eliminates the need for the external row address that is required by drams that do not have cas -before-ras refresh capability. high-z column address valid data out ras v ih v il v ih v il v ih v il v ih v il v oh v ol cas we dq (output) a 0 to a 10 v ih v il dq (input) v ih v il oe high-z ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq)
26 mb81v17805a-60/-60l/-70/-70l t csr t rp t rcs t fcah t asc valid data t wp t chr t frsh t rwl t fcwd t dh t ds t dzc t oed t dzo t oez t oeh t fcac t fcas t cp t cwl t oea t on cas fig. 19 ? cas -before-ras refresh counter test cycle parameter unit min. max. ns no. min. max. 55 50 (at recommended operating conditions unless otherwise noted.) symbol 35 ns 35 77 ns 70 99 ns 90 99 ns 90 mb81v17805a-60/60l mb81v17805a-70/70l access time from cas column address hold time cas to we delay time cas pulse width ras hold time note: assumes that cas -before-ras refresh counter test cycle only. v ih v il v ih v il ras a 0 to a 10 v ih v il v ih v il v ih v il v oh v ol v ih v il we dq (input) oe 69 t fcac t fcah t fcwd t fcas t frsh column addresses description a special timing sequence using the cas -before-ras refresh counter test cycle provides a convenient method to verify the function of cas -before-ras refresh circuitry. if a cas -before-ras refresh cycle cas makes a transition from high to low while ras is held low, read and write operations are enabled as shown above. row and column addresses are de?ed as follows: row address: bits a 0 through a 10 are de?ed by the on-chip refresh counter. column addresses: bits a 0 through a 9 are de?ed by latching levels on a 0 to a 9 at the second falling edge of cas . the cas -before-ras counter test procedure is as follows; 1) initialize the internal refresh address counter by using 8 ras -only refresh cycles. 2) use the same column address throughout the test. 3) write ??to all 2,048 row addresses at the same column address by using normal write cycles. 4) read ??written in procedure 3) and check; simultaneously write ??to the same addresses by using cas -before-ras refresh counter test (read-modify-write cycles). repeat this procedure 2,048 times with addresses generated by the internal refresh address counter. 5) read and check data written in procedure 4) by using normal read cycle for all 2,048 memory locations. 6) reverse test data and repeat procedures 3), 4), and 5). dq (output) high-z high-z valid data in ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) 70 71 72 73
27 mb81v17805a-60/-60l/-70/-70l cas fig. 20 ? self refresh cycle (a 0 to a 11 = we = oe = ? or ?? (at recommended operating conditions unless otherwise noted.) note: assumes self refresh cycle only. parameter unit min. max. no. min. max. 74 100 100 symbol 75 124 104 76 ?0 ?0 m s ns ns ras pulse width ras precharge time cas hold time mb81v17805a-60/60l mb81v17805a-70/70l t rass t rps t chs description the self refresh cycle provides a refresh operation without external clock and external address. self refresh control circuit on chip is operated in the self refresh cycle and refresh operation can be automatically executed using internal refresh address counter and timing generator. if cas goes to ??before ras goes to ??(cbr) and the condition of cas ??and ras ??is kept for term of t rass (more than 100 m s), the device can enter the self refresh cycle. following that, refresh operation is automatically executed at fixed intervals using internal refresh address counter during ?as =l?and ?as =l? exit from self refresh cycle is performed by toggling ras and cas to ??with specified t chs min. in this time, ras must be kept ??with specified t rps min. using self refresh mode, data can be retained without external cas signal during system is in standby. restriction for self refresh operation ; for self refresh operation, the notice below must be considered. 1) in the case that distributed cbr refresh are operated between read/write cycles self refresh cycles can be executed without special rule if 2,048 cycles of distributed cbr refresh are executed within t ref max. 2) in the case that burst cbr refresh or distributed/burst ras -only refresh are operated between read/write cycles 2,048 times of burst cbr refresh or 2,048 times of burst ras -only refresh must be executed before and after self refresh cycles. v ih v il ras v ih v il ras v ih v il v oh v ol dq (output) high-z t rass t rps t rpc t chs t csr t cpn t off t oh * read/write operation can be performed non refresh time within t ns or t sn 2,048 burst refresh cycle 2,048 burst refresh cycle read/write operation self refresh operation read/write operation t ns < 2 ms t rass t sn < 2 ms ? or ? level (excluding address and dq) ? or ? level, ? ? ? or ? ? ? transition (address and dq) * *
28 mb81v17805a-60/-60l/-70/-70l n package dimensions 1994 fujitsu limited c28058s-2c(w) 28-lead plastic leaded chip carrier (case no.: lcc-28p-m07) dimensions in mm (inches) *: resin protrusion (each side : 0.15(.006)max.) C.001 +.002 C0.02 +0.05 C.008 +.014 C0.20 +0.35 * 18.420.13(.725.005) .008 0.20 .134 3.40 (.370.020) 9.400.51 2.75(.108)nom 0.64(.025)min r0.81(.032)typ 0.81(.032)max 0.430.10(.017.004) details of "a" part 2.50(.098)nom 0.10(.004) (.432.005) 10.970.13 (.400) nom 10.16 1 28 15 14 (.050.005) 1.270.13 16.51(.650)ref index "a" lead no
29 mb81v17805a-60/-60l/-70/-70l n package dimensions 1994 fujitsu limited f28040s-1c(w) 28-lead plastic flat package (case no.: fpt-28p-m14) dimensions in mm (inches) *: resin protrusion : (each side : 0.15(.006)max) lead no. "a" 0.15(.006) max 0.50(.020) max 0.15(.006) 0.25(.010) details of "a" part (.005.002) 0.1250.05 (.424.008) 10.760.20 (.020.004) 0.500.10 (.400.004) 10.160.10 (.463.008) 11.760.20 (stand off) 0.05(.002)min 1.150.05(.045.002) 0.10(.004) typ. 1.27(.050) ref. 16.51(.650) * 0.21(.008) m (.016.004) 0.400.10 (.725.004) 18.410.10 index 14 1 15 28
30 mb81v17805a-60/-60l/-70/-70l fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices kawasaki plant, 4-1-1, kamikodanaka nakahara-ku, kawasaki-shi kanagawa 211-88, japan tel: (044) 754-3753 fax: (044) 754-3332 north and south america fujitsu microelectronics, inc. semiconductor division 3545 north first street san jose, ca 95134-1804, u.s.a. tel: (408) 922-9000 fax: (408) 432-9044/9045 europe fujitsu mikroelektronik gmbh am siebenstein 6-10 63303 dreieich-buchschlag germany tel: (06103) 690-0 fax: (06103) 690-122 asia paci? fujitsu microelectronics asia pte. limited #05-08, 151 lorong chuan new tech park singapore 556741 tel: (65) 281-0770 fax: (65) 281-0220 f9611 ? fujitsu limited printed in japan all rights reserved. circuit diagrams utilizing fujitsu products are included as a means of illustrating typical semiconductor applications. com- plete information sufficient for construction purposes is not nec- essarily given. the information contained in this document has been carefully checked and is believed to be reliable. however, fujitsu as- sumes no responsibility for inaccuracies. the information contained in this document does not convey any license under the copyrights, patent rights or trademarks claimed and owned by fujitsu. fujitsu reserves the right to change products or specifications without notice. no part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior written consent of fujitsu. the information contained in this document are not intended for use with equipments which require extremely high reliability such as aerospace equipments, undersea repeaters, nuclear con- trol systems or medical equipments for life support.

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